1. Field of the Invention
The process of the present invention is directed to fabricating an integrated circuit with shallow junctions.
2. Art Background
Design rules for integrated circuits are becoming increasingly small. As integrated circuit dimensions decrease, so do the dimensions of the discrete devices in the integrated circuit. A p-n junction is a typical component of an integrated circuit device. A p-n junction is the internal boundary between a portion of a substrate, typically silicon, that is doped with an n-type material and another portion of a substrate that is doped with a p-type material. The amount of the dopant introduced into the substrate and the depth to which the dopant penetrates into the substrate determines the depth of the junction. As the dimensions of integrated circuits decrease, the junction depths of discrete devices also decrease.
A process for fabricating ultra-shallow junctions in integrated circuit devices are described in Hong, S. N., et al., "Characterization of Ultra-Shallow p.sup.+ -n Junction Diodes Fabricated by 500-eV Boron-Ion Implantation," IEEE Transactions on Electron Devices, 38(1), pp. 28-31 (January 1991). The article describes a low energy method for ion implantation of dopants, and states that the shallowest junction depths obtained by this technique are 0.06 to 0.08 microns. In the described method, boron is ion implanted into the substrate using low (500 eV) energy. This implantation introduces defects into the silicon substrate. The article states that this damage is relatively close to the surface, and these near-surface defects are removed by rapid thermal annealing.
To control junction depth, one must control the amount of dopant introduced into the substrate and the degree to which the dopant penetrates into the substrate. Although ion implantation is typically used to introduce dopants into silicon, it is difficult to control the degree to which the dopants penetrate the silicon using this procedure. As recognized in Ling, E., et al., "Very Shallow Low-Resistivity p.sup.+ -n Junctions for CMOS Technology," IEEE Electron Device Letters, 8(3), pp. 96-97 (1987), ion implantation of dopants such as boron can also cause defects in the substrate. Ling et al. report that junction depths of 0.1 .mu.m or more are obtained if a spin-on dopant source is applied onto a substrate and the substrate is then subjected to rapid thermal annealing to drive the dopant into the substrate.
Spin-on dopant sources are an alternate means to ion implantation for introducing dopants into silicon. Spin-on dopant sources are described in Usami, A., et al. "Shallow Junction Formation for Silicon Solar Cells by Light-induced Diffusion of Phosphorus from a Spin-on Source," Conference Record of the Eighteenth IEEE Photovoltaic Specialists Conference, pp. 797-803 (October 1985), and Ando, M., et al., "Si solar cells fabricated by Incoherent Light-Induced Diffusion of Phosphorus from a Spin-on Source," Technical Digest of the International PVSEC-1, pp. 67-70 (November 1984). Dopant is introduced into the silicon from the spin-on dopant source by diffusion from the spin on dopant source into the silicon. These dopant sources are termed "spin-on" because they are spun on the substrate as a film.
Usami et al. describe a process in which a Phosphorus (P)-doped oxide film is spun onto a substrate. The substrate is then subjected to a rapid thermal diffusion process to drive the dopant into the substrate. Usami et al. report that a stress field is induced by the difference of thermal expansion coefficient between oxide films and silicon. Ando et al. also describe a process in which a P-doped oxide film is spun onto a substrate. Ando et al. report that junction depths in excess of 0.1 .mu.m were obtained by subjecting substrates on which a spin-on dopant source was applied to incoherent light annealing.
The doping of junctions with a depth of 0.02 microns is disclosed in Hartiti, B., "Phosphorus Diffusion into Silicon from a Spin-on Source Using Rapid Thermal Processing," Journal of Applied Physics, 71(11), pp. 5474-5478 (June 1992). The reference describes spinning a 2000 .ANG. thick phosphorus-doped silicon film (a spin on dopant source) on a substrate. The substrate has a layer of silicon dioxide over certain discrete areas of the surface. The oxide prevents the dopant from permeating into the portion of the substrate underlying the oxide. This oxide is referred to as the field oxide and, because of its insulating properties, it plays an important role in device performance as well as device fabrication. Haiti et al. describes subjecting the substrate to rapid isothermal processing at 800.degree. C. to 1000.degree. C. for between 5 and 120 seconds under a pure argon flow to drive the dopant into the substrate. Haiti et al. report that the film was removed by a 5 minute hydrofluoric acid (HF) cleaning.
HF dissolves silicon dioxide. Therefore, it is likely that a portion of the field oxide adjacent to the film will also be dissolved if an HF etchant is used to remove the film of spin-on dopant source from the substrate. In devices with shallow junctions, the field oxide is commensurately thin. Consequently, any etching of the field oxide significantly reduces the amount of field oxide left on the device. Because of the importance of the oxide in device performance, a process for fabricating a device with shallow junctions under conditions that do not remove a significant amount of the field oxide is therefore desired.